Two-Gate Transistor for the Study of Si/SiO2 Interface in Silicon-on-Insulator Nano-Channel and Nanocrystalline Si Memory Device
Two-Gate Transistor for the Study of Si/SiO2 Interface in Silicon-on-Insulator Nano-Channel and Nanocrystalline Si Memory Device
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用于研究绝缘体上硅纳米通道和纳米晶硅存储器件中 Si/SiO2 界面的双栅极晶体管
DOI：
10.1143/jjap.39.4637
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发表时间：
2000
影响因子：
1.5
通讯作者：
S. Oda
中科院分区：
文献类型：
--
作者：
B. Hinds;K. Nishiguchi;A. Dutta;T. Yamanaka;S. Hatanani;S. Oda
一种活性面积为1.5×10-10 cm2的双栅单电子存储器件，可以研究绝缘体上硅（SOI）和纳米晶硅（nc-Si）点纳米通道中的Si/SiO2界面。该装置的基础是在一个大的“倒置”栅极内定义一个沟槽（150 - 600nm宽），其中可以通过远程等离子体增强化学气相沉积沉积nc-Si（8±1nm直径）。通过泊松方程和连续方程的二维和三维数值模拟对器件结构进行了分析，结果表明通道表面电位均匀。该器件设计允许调整阈值移位，以及控制65-165nm的有源区域长度，并施加栅极偏置。这允许通道上带电界面缺陷以及存储在nc-Si中的电荷的可量化阈值移位。根据沿30nm宽通道宽度的带电物质的位置，计算70 - 120mv之间的阈值移位。为了研究单个缺陷位点的能级，有或没有沉积nc-Si的带电位点的寿命研究是可能的。
A two-gate single electron memory device with active area of 1.5×10-10 cm2 allows the study of Si/SiO2 interface in nano-scale channels of silicon on insulator (SOI) and nanocrystalline Si (nc-Si) dots. The basis of this device is a trench (150–600 nm wide) defined inside a large “inversion” gate electrode into which nc-Si (8±1 nm diameter) can be deposited by remote plasma enhanced chemical vapor deposition. Device structure is analyzed with 2-D and 3-D numerical simulation of Poisson's and continuity equations, which show uniform surface potential of channel. The device design allows for tuning of threshold shifts as well as controlling the length of active area from 65–165nm with applied gate bias. This allows for quantifiable threshold shifts for charged interface defects on the channel as well as charge stored in nc-Si. Threshhold shifts of between 70–120 mV are calculated depending on the location of charged species along the width of the 30nm wide channel. To study energy levels of single defect sites, lifetime studies of charged sites are possible with and without deposited nc-Si.