eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
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DOI：
10.1049/iet-cdt.2013.0087
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发表时间：
2014-06
期刊：
影响因子：
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通讯作者：
A. Beldachi;S. Hollis;J. Núñez-Yáñez
中科院分区：
文献类型：
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作者：
A. Beldachi;S. Hollis;J. Núñez-Yáñez
本文提出了一种新的路由算法——扩展环面路由算法，该算法支持基于可变数量和大小的内环面构建块的拓扑结构。将传统的网状网络内环划分为任意数量的子网，以提高网状网络的性能。子网可以生成非规则的全局拓扑结构，XTRANC算法也支持这种拓扑结构。XTRANC特别适用于映射到商业fpga的动态可重构网络，其中在运行时将额外的链路添加到网状拓扑中，以减少依赖于应用程序行为和资源可用性的拥堵。XTRANC允许根据应用程序的不同部分的请求插入链接，而不需要集中控制，这项研究表明，尽管有这种动态行为，路由算法仍然没有死锁。
This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.