Designing a 2048-Chiplet, 14336-Core Waferscale Processor
Designing a 2048-Chiplet, 14336-Core Waferscale Processor
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DOI：
10.1109/dac18074.2021.9586194
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发表时间：
2021-12
期刊：
影响因子：
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通讯作者：
Saptadeep Pal;Jingyang Liu;Irina Alam;Nicholas Cebry;Haris Suhail;Shi Bu;S. Iyer;S. Pamarti;Rakesh Kumar;Puneet Gupta
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文献类型：
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作者：
Saptadeep Pal;Jingyang Liu;Irina Alam;Nicholas Cebry;Haris Suhail;Shi Bu;S. Iyer;S. Pamarti;Rakesh Kumar;Puneet Gupta
晶圆级处理器系统可以提供当今高度并行工作负载所需的大量内核和内存带宽。构建晶圆级系统的一种方法是使用基于小芯片的架构，其中预测试的小芯片集成在无源硅互连晶圆上。该技术允许异构集成，并可提供显著的性能和成本优势。然而，设计这样一个系统有几个挑战，如功率输送，时钟分配，晶圆级网络设计，可测试性和容错设计。在这项工作中，我们讨论了这些挑战和解决方案，我们采用设计一个2048芯片，14,336核晶圆级处理器系统。
Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the solutions we employed to design a 2048-chiplet, 14,336-core waferscale processor system.