Overview of the SpiNNaker System Architecture
Overview of the SpiNNaker System Architecture
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DOI：
10.1109/tc.2012.142
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发表时间：
2013-12-01
影响因子：
3.7
通讯作者：
Brown, Andrew D.
中科院分区：
文献类型：
--
作者：
Furber, Steve B.;Lester, David R.;Brown, Andrew D.
SpiNNaker（Spiking Neural Network Architecture的缩写）是一个百万核计算引擎，其旗舰目标是能够在真实的时间内模拟多达10亿个神经元的聚合行为。它由一系列ARM9内核组成，通过自定义互连结构携带的数据包进行通信。数据包很小（40或72位），它们的传输完全由硬件代理，使整个引擎具有超过50亿个数据包/秒的极高二分带宽。并行机设计的三个主要公理（内存一致性，同步性和确定性）在设计中被丢弃，而不会令人惊讶地损害执行有意义计算的能力。该系统的另一个属性是，从最初的设计阶段就认识到，实现的庞大规模将使组件故障成为日常操作中不可避免的一个方面，并且故障检测和恢复机制已在许多抽象级别上内置于系统中。本文描述了机器的架构，并概述了基本的设计理念;软件和应用程序将在其他地方详细描述，并在必要时仅在这里顺便介绍，以阐明说明。
SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behavior of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware, giving the overall engine an extremely high bisection bandwidth of over 5 billion packets/s. Three of the principal axioms of parallel machine design (memory coherence, synchronicity, and determinism) have been discarded in the design without, surprisingly, compromising the ability to perform meaningful computations. A further attribute of the system is the acknowledgment, from the initial design stages, that the sheer size of the implementation will make component failures an inevitable aspect of day-to-day operation, and fault detection and recovery mechanisms have been built into the system at many levels of abstraction. This paper describes the architecture of the machine and outlines the underlying design philosophy; software and applications are to be described in detail elsewhere, and only introduced in passing here as necessary to illuminate the description.