An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform
An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform
复制标题
DOI：
10.1109/fccm.2019.00063
复制
发表时间：
2019-04
期刊：
影响因子：
--
通讯作者：
Samah Rahamneh;L. Sawalha
中科院分区：
文献类型：
--
作者：
Samah Rahamneh;L. Sawalha
现场可编程门阵列（fpga）为异构系统提供性能和功耗优势。在这项工作中，我们使用一个紧密耦合的CPU-FPGA异构系统来加速Canny边缘检测器算法，并将混合实现与优化的CPU和FPGA单独实现的性能进行了比较。我们的结果显示，混合实现比仅CPU实现的速度提高了4.8倍，比仅FPGA实现的速度提高了2.1倍。
Field programmable gate arrays (FPGAs) provide both performance and power benefits to heterogeneous systems. In this work, we used a closely-coupled CPU-FPGA heterogeneous system to accelerate Canny edge detector algorithm and compared the performance of the hybrid implementation with that of the optimized separate CPU and FPGA implementations. Our results show up to 4.8X speedup for the hybrid implementation over the CPU only implementation and up to 2.1X over the FPGA only implementation.