A novel renaming scheme to exploit value temporal locality through physical register reuse and unification
A novel renaming scheme to exploit value temporal locality through physical register reuse and unification
复制标题
一种新颖的重命名方案，通过物理寄存器重用和统一来利用值时间局部性
DOI：
--
复制
发表时间：
1998
期刊：
影响因子：
--
通讯作者：
Adi Yoaz
中科院分区：
文献类型：
--
作者：
S. Jourdan;R. Ronen;Michael Bekerman;Bishara Shomar;Adi Yoaz
硬件重命名方案为每个逻辑名称提供多个物理位置（寄存器或存储器）。在当前的重命名方案中，为每个分派的指令分配新的物理位置，而不管其结果值如何。然而，这些值表现出高水平的时间局部性（结果冗余）。本文提出：物理寄存器复用。只要检测到传入的结果值与前一个结果值匹配，就重用物理位置。这是在寄存器重命名期间执行的，需要一些值标识检测硬件。物理寄存器复用通过将存储相同值的多个逻辑寄存器映射到同一个物理寄存器，提供了以下机会：共享-利用寄存器文件中的高级别值冗余来减小文件大小和复杂性，或者有效地扩大活动指令窗口。我们的研究结果表明，在某些情况下，减少因子为2至4。通过扩大指令窗口或通过需要较少端口的较小寄存器文件实现的较高频率来提高性能。结果重用和依赖重定向-将生成结果的责任从功能单元转移到寄存器重命名器，从而可能从执行流中消除已处理的指令。(2)从一条指令到较早的指令流，可能允许指令被更早地调度。通过这种方式，实现了大的性能加速。2.统一。将存储器重命名器与寄存器重命名器进行联合收割机组合，以便将上述共享和结果重用以及依赖性重定向思想扩展到寄存器和存储器位置两者。这样可以节省更多的硬件并提高性能。这也简化了存储指令的处理。
Hardware renaming schemes provide multiple physical locations (register or memory) for each logical name. In current renaming schemes, a new physical location is allocated for each dispatched instruction regardless of its result value. However, these values exhibit a high level of temporal locality (result redundancy). This paper proposes: Physical Register Reuse. To reuse a physical location whenever it is detected that an incoming result value matches a previous one. This is performed during register renaming and requires some VALUE-IDENTITY DETECTION hardware. By mapping several logical registers holding the same value to the same physical register, Physical Register Reuse gives the opportunities: SHARING-exploit the high level of value-redundancy in the register file to either reduce the file size and complexity, or effectively enlarge the active instruction window. Our results suggest reduction factors of 2 to 4 in some cases. Performance is increased either by the enlarged instruction window or by the higher frequency enabled by a smaller register file requiring fewer ports. RESULT REUSE AND DEPENDENCY REDIRECTION-move the responsibility of generating results: (1) From the functional units to the register renamer, resulting in the possible elimination of processed instructions from the execution stream. (2) From one instruction to an earlier instruction stream, possibly allowing instructions to be scheduled earlier. This way, large performance speedups are achieved. 2. Unification. To combine the memory renamer with the register renamer in order to extend the above-stated sharing and result reuse and dependency redirection ideas to both registers and memory locations. This allows even greater hardware savings and performance improvements. This also simplifies the processing of store instructions.