PoweRock: Power Modeling and Flexible Dynamic Power Management for Many-Core Architectures
PoweRock: Power Modeling and Flexible Dynamic Power Management for Many-Core Architectures
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DOI：
10.1109/jsyst.2015.2499307
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发表时间：
2017-06
影响因子：
4.4
通讯作者：
Zhiquan Lai;King Tin Lam;Cho-Li Wang;Jinshu Su
中科院分区：
文献类型：
--
作者：
Zhiquan Lai;King Tin Lam;Cho-Li Wang;Jinshu Su
Energy-efficient design for green high-performance computing (HPC) is a formidable mission for today’s computer scientists. Dynamic power management (DPM) is a key enabling technology involved. While DPM can have various goals for different application scenarios (e.g., enforcing an upper bound on power consumption or optimizing energy usage under a performance-loss constraint), existing DPM solutions are generally designed to meet only one goal and not adaptable to changes in optimization objectives. This paper proposes a novel flexible DPM approach based on a profile-guided dynamic voltage/frequency scaling (DVFS) scheme to meet the different goals. Our contributions include 1) an accurate power prediction model for many-core architectures; 2) a new profiling method for (distributed) shared-memory parallel applications to flexibly determine the optimal frequency and voltage for different phases of the execution; and 3) a hierarchical domain-aware power control design boosting the DPM system scalability for many-core chips. We implement the approach into a working library dubbed PoweRock and evaluate it on the Intel SCC port of the Barrelfish operating system. Experimental results obtained from several well-known benchmarks show that PoweRock attains significant energy and energy-delay product (EDP) improvements (average: 37.1% and 25.5%; best case: 64.0% and 65.4%, respectively) over a static power scheme.
