Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)
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DOI：
10.1109/tvlsi.2009.2035509
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发表时间：
2011-03
影响因子：
2.8
通讯作者：
W. Xu;Hongbin Sun;Xiaobin Wang;Yiran Chen;Tong Zhang
中科院分区：
文献类型：
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作者：
W. Xu;Hongbin Sun;Xiaobin Wang;Yiran Chen;Tong Zhang
由于其具有上级可扩展性的高存储密度、低集成成本和相当高的存取速度，自旋扭矩转移随机存取存储器（STT RAM）似乎具有替代SRAM作为末级片上高速缓存（例如，L2或L3高速缓存）。由于其存储器件磁隧道结（MTJ）的独特操作特性，STT RAM固有地经受由存储器单元大小确定的写入延迟与读取延迟的权衡。本文首先定量研究了不同的存储单元大小可能会影响整体计算系统的性能，并表明，不同的计算工作负载可能有冲突的期望存储单元大小。利用MTJ器件的开关特性，我们进一步提出了一种STT RAM架构的设计方法，可以使STT RAM缓存与相对较小的存储单元的大小表现良好，在广泛的计算基准。这已经通过基于CACTI的内存建模和使用SimpleScalar的计算系统性能模拟得到了很好的证明。此外，我们表明，这种设计方法也可以减少STT RAM缓存的能源消耗高达30%，在各种基准。
Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing. Leveraging MTJ device switching characteristics, we further propose an STT RAM architecture design method that can make STT RAM cache with relatively small memory cell size perform well over a wide spectrum of computing benchmarks. This has been well demonstrated using CACTI-based memory modeling and computing system performance simulations using SimpleScalar. Moreover, we show that this design method can also reduce STT RAM cache energy consumption by up to 30% over a variety of benchmarks.