Integration of threshold logic gates with RRAM devices for energy efficient and robust operation
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation
复制标题
将阈值逻辑门与 RRAM 器件集成，实现节能和稳健运行
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
S. Vrudhula
中科院分区：
文献类型：
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作者：
Jinghua Yang;Niranjan S. Kulkarni;Shimeng Yu;S. Vrudhula
差分模式阈值逻辑门可以被编程为在单个单元内计算复杂的逻辑函数，从而显著减小面积和功率。然而，如果它们在低电压下操作，则电路成品率降低。本文介绍了一种新的集成RRAM与这样的阈值逻辑门，以实现鲁棒性，低电压（0.6V的65纳米技术）和节能计算的阈值逻辑功能。低于0.6V，我们观察到，传统的CMOS电路的性能（从而，能量延迟产品）大幅下降相比，所提出的阈值逻辑电路。在考虑MOSFET和RRAM器件的工艺变化的同时，证明了新的电路结构在性能和能量方面的改进。对于每一个阈值逻辑门实现的阈值功能，能量，延迟和能量延迟产品与等效的CMOS实现的比较。通过两种常用的功能元件，证明了阈值逻辑实现相对于传统CMOS逻辑门在面积、功耗和延迟方面的优势。
Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.