The Design Space of Register Renaming Techniques
The Design Space of Register Renaming Techniques
复制标题
寄存器重命名技术的设计空间
作者：
D. Sima
寄存器重命名是一种消除错误数据相关性的技术--读后写(WAR)和写后写(WAW)--它们出现在后续指令的寄存器操作数之间的直线代码中。通过消除指令执行序列中的相关优先级要求，重命名增加了每个周期可用于并行执行的平均指令数。这会导致增加的IPC(每个周期执行的指令数量)。对寄存器重命名设计空间的识别和探索使我们对这一复杂的技术有了全面的了解。如本文所示，寄存器重命名的设计空间主要由四个维度组成：寄存器重命名的范围、重命名缓冲区的布局、寄存器映射的方法和重命名率。设计空间的相关方面产生了寄存器重命名的八种基本选择。此外，操作数获取策略的类型显著影响处理器如何执行重命名过程，这复制了16个可能的实现方案的8个基本备选方案。文章指出了在相关的超标量处理器中采用的基本实现方案。由于寄存器重命名通常与搁置一起实现，因此假定底层微体系结构使用搁置。
Register renaming is a technique to remove false data dependencie-write after read (WAR) and write after write (WAW)-that occur in straight line code between register operands of subsequent instructions. By eliminating related precedence requirements in the execution sequence of the instructions, renaming increases the average number of instructions that are available for parallel execution per cycle. This results in increased IPC (number of instructions executed per cycle). The identification and exploration of the design space of register-renaming lead to a comprehensive understanding of this intricate technique. As this article shows, the design space of register renaming is spanned by four main dimensions: the scope of register renaming, the layout of the rename buffers, the method of register mapping, and the rename rate. Relevant aspects of the design space give rise to eight basic alternatives for register-renaming. In addition, the kind of operand fetch policy significantly affects how the processor carries out the rename process, which duplicates the eight basic alternatives to 16 possible implementation schemes. The article indicates which basic implementation scheme is used in relevant superscalar processors. As register renaming is usually implemented in conjunction with shelving, the underlying microarchitecture is assumed to employ shelving.