A 13.4-GHz CMOS frequency divider
A 13.4-GHz CMOS frequency divider
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13.4GHz CMOS 分频器
DOI：
10.1109/isscc.1994.344680
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
R. Yan
中科院分区：
文献类型：
--
作者：
B. Razavi;Kwing F. Lee;R. Yan
本文描述了一种13.4 GHz 1/2分频器的设计，该分频器采用部分规模的0.1/spl mU/m体硅工艺。电路设计很大程度上受器件结构和布局规则的影响。为了同时降低制造成本和周转时间，CMOS工艺仅将沟道长度调整为0.1/splµ/m，将栅氧化层调整为40/spl aring/。其他尺寸的设计规则对应于1/splµ/m工艺，产生的最小源极/漏极面积为2.2/spl×/2.2/spl亩/m/sup 2/。因此，源极/漏极结电容的贡献是相当大的，严重限制了速度。所描述的除法器采用以下技术来提高速度：1)用于传感和再生的nMOSFET和用于上拉的pMOSFET，2)没有堆叠的器件和通过门，3)所有晶体管的环形几何结构。
This paper describes the design ofa 13.4 GHz 1/2-frequency divider fabricated in a partially-scaled 0.1 /spl mu/m bulk CMOS technology. The circuit design is heavily influenced by the device structures and layout rules. To reduce both fabrication cost and turnaround time, the CMOS process scales only channel length to 0.1 /spl mu/m and gate oxide to 40 /spl Aring/. Design rules for other dimensions correspond to a 1 /spl mu/m technology, yielding a minimum source/drain area of 2.2 /spl times/2.2 /spl mu/m/sup 2/. Thus the contribution of the source/drain junction capacitance is substantial, severely limiting speed. The divider described employs the following techniques to improve the speed: 1) nMOSFETs for sensing and regeneration and pMOSFETs for pull-up, 2) no stacked devices and pass gates, 3) ring-shaped geometry for all transistors.<<ETX>>