FPGA Implementations of Feed Forward Neural Network by using Floating Point Hardware Accelerators
FPGA Implementations of Feed Forward Neural Network by using Floating Point Hardware Accelerators
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使用浮点硬件加速器的 FPGA 实现前馈神经网络
DOI：
10.15598/aeee.v12i1.831
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发表时间：
2014
影响因子：
0.6
通讯作者：
A. Salvini
中科院分区：
文献类型：
--
作者：
G. Lozito;Antonino Laudani;F. R. Fulginei;A. Salvini
本文记录了通过使用浮点加速器在FPGA设计上实施偏差解决方案的分析的研究。特别是，研究了两个不同的实现：在软处理器设计上创建神经网络的高级解决方案，并采用了增强流程性能的不同策略；一个低水平的解决方案，通过浮点算术元件的case来实现。介绍了在架构中使用的时间消耗和FPGA资源方面所达到的性能的比较。
This paper documents the research towards the analysis of dierent solutions to implement a Neu- ral Network architecture on a FPGA design by using floating point accelerators. In particular, two dierent implementations are investigated: a high level solution to create a neural network on a soft processor design, with dierent strategies for enhancing the performance of the process; a low level solution, achieved by a cas- cade of floating point arithmetic elements. Compar- isons of the achieved performance in terms of both time consumptions and FPGA resources employed for the architectures are presented.