Buffer Reduction via N-Phase Clocking in Adiabatic Quantum-Flux-Parametron Benchmark Circuits
Buffer Reduction via N-Phase Clocking in Adiabatic Quantum-Flux-Parametron Benchmark Circuits
复制标题
通过绝热量子通量参量管基准电路中的 N 相时钟减少缓冲区
DOI：
10.1109/tasc.2021.3073837
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发表时间：
2021
影响因子：
1.8
通讯作者：
Yoshikawa Nobuyuki
中科院分区：
文献类型：
--
作者：
Saito Ro;Ayala Christopher Lawrence;Yoshikawa Nobuyuki
绝热量子通量参变逻辑(AQFP)是一种能够产生极低能量计算系统的超导逻辑家族。然而，AQFP电路在投入实际应用之前还有一些挑战需要克服，提高电路集成度就是其中之一。传统上，四相时钟分布被用作AQFP电路的功率时钟网络。这种方法需要门在相邻相上传输数据信号电流。四相时钟的缺点不仅是由于在单个周期内将信号传播限制到四级逻辑而导致的大延迟，而且还在于大型电路所需的大量信号缓冲。缓冲占用了芯片上宝贵的面积。我们提出了采用n相时钟的方法，不仅可以减少AQFP电路的延迟，还可以减少n大于4的缓冲器数目。当每个时钟周期的相数增加x倍时，我们证明了在许多AQFP基准电路中，缓冲器数目可以减少到1/x倍。
Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family capable of producing extremely low-energy computing systems. However, AQFP circuitry has some challenges to overcome before it can go into practical use, and improving circuit integration is one of them. Conventionally, a four-phase clocking distribution has been utilized as the power-clock network for AQFP circuits. This method requires gates to transmit data signal currents on adjacent phases. The drawback to four-phase clocking is not only the large latency due to limiting signal propagation to four-stages of logic in a single cycle, but also the enormous amount of signal buffering that is required for large circuits. Buffering uses up valuable area on the chip. We propose the adoption of an n-phase clocking method to not only reduce the latency of AQFP circuits but to also reduce the number of buffers for n larger than 4. When the number of phases per clock cycle increases by x times, we show that the number of buffers can be decreased to 1/x times in a number of AQFP benchmark circuits.