Coding for systern-on-chip networks: a unified framework
Coding for systern-on-chip networks: a unified framework
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DOI：
10.1145/996566.996600
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发表时间：
2004-06
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影响因子：
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通讯作者：
S. Sridhara;Naresh R Shanbhag
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文献类型：
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作者：
S. Sridhara;Naresh R Shanbhag
在本文中，我们提出了一种编码框架，源自DSM总线的通信理论观点，以共同解决功率，延迟和可靠性问题。在此框架中，数据首先通过非线性源编码器传递，该编码器减少了自身和耦合转换活动，并对总线上的峰值耦合转换施加了约束。接下来，一个线性错误控制编码器增加冗余，使错误检测和纠正。该框架用于有效地结合现有代码并获得新的代码，这些代码跨越总线延迟，编解码器延迟，功耗，面积和可靠性之间的广泛权衡。对0.18 μm CMOS技术的l-cm 32 hit总线的仿真结果表明，可以实现31%的能量降低和62%的能量延迟产品降低。
In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently conibine existing codes and to derive novel, codes that span a wide range of trade-offs between bus delay, codec latency, power, area, and reliability, Simulation results, for a l-cm 32-hit bus in a 0.18-μm CMOS technology, show that 31% reduction in energy and 62% reduction in enkrgy-delay product are achievable.