NDS: N-Dimensional Storage
NDS: N-Dimensional Storage
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DOI：
10.1145/3466752.3480122
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发表时间：
2021-10
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影响因子：
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通讯作者：
Yu-Chia Liu;Hung-Wei Tseng
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文献类型：
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作者：
Yu-Chia Liu;Hung-Wei Tseng
使用高维数据集的应用程序对高效计算的需求导致了多维计算机——利用异构处理器/加速器提供各种处理模型来支持多维计算内核的计算机。然而，这些处理器/加速器的前端是低效的，因为内存/存储系统通常只向应用程序公开根深蒂固的线性空间抽象，并且它们经常忽略现代内存/存储系统的好处，例如通过不同类型的并行访问支持多维。n维存储（NDS）是一种满足现代硬件加速器和应用需求的新型多维存储系统。NDS将内存数组抽象为应用程序可以用来描述数据位置的本机存储，并使用任何应用程序定义的多维空间中的坐标，从而避免了与数据对象转换相关的软件开销。NDS衡量内存设备架构下的应用程序需求，以便智能地确定物理数据布局，从而最大化访问带宽并最小化为任意应用程序呈现对象的开销。本文展示了一种支持NDS的高效体系结构。我们在使用每种架构的定制系统上评估一组线性/张量代数工作负载以及图和数据挖掘算法。我们的结果显示，在适当的体系结构支持下，速度提高了5.73倍。
Demands for efficient computing among applications that use high-dimensional datasets have led to multi-dimensional computers—computers that leverage heterogeneous processors/accelerators offering various processing models to support multi-dimensional compute kernels. Yet the front-end for these processors/accelerators is inefficient, as memory/storage systems often expose only entrenched linear-space abstractions to an application, and they often ignore the benefits of modern memory/storage systems, such as support for multi-dimensionality through different types of parallel access. This paper presents N-Dimensional Storage (NDS), a novel, multi-dimensional memory/storage system that fulfills the demands of modern hardware accelerators and applications. NDS abstracts memory arrays as native storage that applications can use to describe data locations and uses coordinates in any application-defined multi-dimensional space, thereby avoiding the software overhead associated with data-object transformations. NDS gauges the application demand underlying memory-device architectures in order to intelligently determine the physical data layout that maximizes access bandwidth and minimizes the overhead of presenting objects for arbitrary applications. This paper demonstrates an efficient architecture in supporting NDS. We evaluate a set of linear/tensor algebra workloads along with graph and data-mining algorithms on custom-built systems using each architecture. Our result shows a 5.73 × speedup with appropriate architectural support.