Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses
Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses
复制标题
利用硬件事务内存进行缓存侧通道防御
DOI：
10.1145/3196494.3196501
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Xiaofeng Wang
中科院分区：
文献类型：
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作者：
Sanchuan Chen;Fangfei Liu;Zeyu Mi;Yinqian Zhang;R. Lee;Haibo Chen;Xiaofeng Wang
程序使用CPU缓存可能会揭示其内存访问模式，从而在程序执行秘密依赖性内存访问时泄漏敏感信息。在最近的研究中，已经证明，可以在各种情况下进行观察受害者计划的缓存用途来提取秘密的缓存侧向通道攻击，其中最令人担忧的是交叉VM攻击和针对SGX Enclaves的攻击。在本文中，我们提出了一种利用硬件交易内存（HTM）的机制，以使软件程序能够为自己的各种缓存侧通道攻击辩护。我们观察到，当HTM通过改造高速缓存相干协议实现时，就像英特尔的交易同步扩展一样，在高速缓存侧通道攻击中必不可少的缓存干扰将不可避免地终止硬件交易。我们对仅限软件解决方案必须满足的安全要求进行系统分析，以打败高速缓存攻击，提出了一种软件设计，该软件设计利用HTM满足这些要求，并在我们的实施中设计了几种优化技术，以减少交易中止造成的绩效影响。经验评估表明，基于HTM的解决方案引起的性能开销很低。
A program's use of CPU caches may reveal its memory access pattern and thus leak sensitive information when the program performs secret-dependent memory accesses. In recent studies, it has been demonstrated that cache side-channel attacks that extract secrets by observing the victim program's cache uses can be conducted under a variety of scenarios, among which the most concerning are cross-VM attacks and those against SGX enclaves. In this paper, we propose a mechanism that leverages hardware transactional memory (HTM) to enable software programs to defend themselves against various cache side-channel attacks. We observe that when the HTM is implemented by retrofitting cache coherence protocols, as is the case of Intel's Transactional Synchronization Extensions, the cache interference that is necessary in cache side-channel attacks will inevitably terminate hardware transactions. We provide a systematic analysis of the security requirements that a software-only solution must meet to defeat cache attacks, propose a software design that leverages HTM to satisfy these requirements and devise several optimization techniques in our implementation to reduce performance impact caused by transaction aborts. The empirical evaluation suggests that the performance overhead caused by the HTM-based solution is low.