A new digital-analog multiplex method using an adder circuit.
A new digital-analog multiplex method using an adder circuit.
复制标题
一种使用加法器电路的新型数模复用方法。
DOI：
10.1088/1748-0221/10/03/c03048
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发表时间：
2015
影响因子：
1.3
通讯作者：
and H. Takahashi.
中科院分区：
文献类型：
--
作者：
Nakamura;Y.;K. Shimazoe;and H. Takahashi.
在本文中，我们提出了一种新的复用方法的时间超过阈值（ToT）的方法，使用加法器电路编码的脉冲高度的信道信息。所提出的方法是多值逻辑（MVL）和辐射探测系统的ToT方法的组合。为了验证该方法的有效性，将12 mm× 12 mm × 12 mm单片GAGG晶体安装在像素尺寸为3 mm× 3 mm的16通道HAMAMATSU MPPC上，加法器电路的输入电阻设置为2 kΩ、4 kΩ、8 kΩ、16 kΩ等，反馈电阻设置为1 kΩ。因此，对于ch 1、ch 2、ch 3、ch 4，输出电压分别变为1/2、1/4、1/8、1/8。成功验证了对应于16值逻辑的4通道输入多路复用。然而，由于振铃和过冲等噪声因素，对应于256值逻辑的8通道输入多路复用器未得到验证。因此，需要一种新的解码算法或噪声切割电路。
In this paper, we propose a new multiplex method for the Time-over-Threshold (ToT) method using an adder circuit to encode channel information in the pulse height. The proposed method is a combination of Multiple-Valued-Logic (MVL) and the ToT method for radiation-detection systems. In order to validate the method, a 12 mm× 12 mm× 12 mm monolithic GAGG crystal was mounted on a 16ch HAMAMATSU MPPC, whose pixel size was 3 mm× 3 mm. The input resistors of the adder circuit were set at 2 kΩ, 4 kΩ, 8 kΩ, 16 kΩ, and so on, and the feedback resistor was set at 1 kΩ. Therefore, the output voltage becomes 1/2, 1/4, 1/8,⋅⋅⋅, for ch1, ch2, ch3,⋅⋅⋅, respectively. A 4ch-input multiplex, which corresponds to 16-valued logic, was successfully verified. However, an 8ch-input multiplex corresponding to 256-valued logic was not verified, owing to noise factors such as ringing and overshoot. Therefore, a new decoding algorithm or a noise-cutting circuit is needed.