11.1 A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation
11.1 A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation
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11.1%20A%20Direct%2012V/24V-to-1V%203W%2091.2%-效率%20Tri-State%20DSD%20Power%20Converter%20with%20Online%20VCF%20Rebalancing%20and%20In-Situ%20Precharge%20Rate%20Regulation
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
D. Ma
中科院分区：
文献类型：
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作者：
Kang Wei;Y. Ramadass;D. Ma
在工业和汽车应用中，12 V/24V电源系统被广泛使用。在这样的系统中，高降压DC-DC转换器非常需要将宽范围的电流直接输送到负载点，以实现高功率密度和效率[1]。在这种情况下，传统的半桥拓扑面临着极短的导通时间和高侧和低侧开关之间的高度不平衡的功率损耗的严峻挑战。另一方面，开关电容（SC）拓扑在电流处理能力和离散转换比（CR）方面表现出明显的缺点。最近，已经提出了混合拓扑结构，以在前端使用SC拓扑结构来降低功率器件上的高VIN电压应力，然后在后端使用电感拓扑结构来提供电流。因此，电感器尺寸可以大大减小以提高系统密度，并且低额定电压器件用于高效率和快速切换。在混合拓扑中，3电平[2]和双降压（DSD）拓扑[3]是常见的例子，如图11.1.1所示。然而，三电平拓扑使用两个低侧开关来对电感器放电，这大大增加了高输入电压（VIN）和CR的导通损耗。另一方面，增加VIN会对DSD拓扑中的开关SH 2施加高电压应力，从而损害可靠性。在高开关频率下，两种拓扑结构的导通时间都很短，这使得栅极驱动和反馈环路设计在高CR下极具挑战性。
In industrial and automotive applications, 12V/24V power systems are widely used. In such systems, high step-down DC-DC converter is highly desirable to deliver a wide range of current directly to the point of load for high power density and efficiency [1]. In this scenario, the conventional half-bridge topology faces severe challenges of extremely short on-time and highly unbalanced power losses between high-side and low-side switches. On the other hand, switched-capacitor (SC) topologies exhibit obvious drawbacks on insufficient current handling and discrete conversion ratios (CRs). Recently, Hybrid topologies have been presented to use SC topology at the front-end to lower the high VIN voltage stress across power devices, and then use inductive topology at the back-end for current delivery. Accordingly, the inductor size can be greatly reduced to improve system density and low voltage rating devices are used for high efficiency and fast switching. Among hybrid topologies, 3-level [2] and double step-down (DSD) topologies [3] are popular examples, as shown in Fig. 11.1.1. However, 3-level topology uses two low-side switches to discharge inductor, largely increasing conduction loss for high input voltage (VIN) and CR. On the other hand, increasing VIN imposes high voltage stress on switch SH2 in DSD topology, compromising the reliability. At high switching frequency, very short on-times in both topologies make gate drive and feedback loop design highly challenging at high CRs.