On the Design of a Photonic Network-on-Chip
On the Design of a Photonic Network-on-Chip
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DOI：
10.1109/nocs.2007.35
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发表时间：
2007-05
期刊：
影响因子：
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通讯作者：
A. Shacham;K. Bergman;L. Carloni
中科院分区：
文献类型：
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作者：
A. Shacham;K. Bergman;L. Carloni
最近纳米级硅-光子集成电路的显著进步，特别是与cmos制造兼容，为在芯片上通信基础设施中利用光技术的独特能力创造了新的机会。基于这些纳米光子构建块，我们考虑了一种光子片上网络体系结构，旨在利用光域中数据交换所带来的巨大传输带宽、低延迟和低功耗。该新颖的体系结构方法采用由电子覆盖控制网络以分布式方式驱动的宽带光子电路交换网络，该电子覆盖控制网络也用于短消息的独立交换。我们解决了芯片多处理器(CMP)应用中插入的关键网络设计问题，包括拓扑结构、路由算法、路径建立和拆除过程以及死锁避免。仿真结果表明，这种光子片上网络使cmp芯片内通信系统的性能有了很大的飞跃，在消耗最小功率的情况下提供了低延迟和超高吞吐量。
Recent remarkable advances in nanoscale silicon-photonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the unique capabilities of optical technologies in the on-chip communications infrastructure. Based on these nano-photonic building blocks, we consider a photonic network-on-chip architecture designed to exploit the enormous transmission bandwidths, low latencies, and low power dissipation enabled by data exchange in the optical domain. The novel architectural approach employs a broadband photonic circuit-switched network driven in a distributed fashion by an electronic overlay control network which is also used for independent exchange of short messages. We address the critical network design issues for insertion in chip multiprocessors (CMP) applications, including topology, routing algorithms, path-setup and tear-down procedures, and deadlock avoidance. Simulations show that this class of photonic networks-on-chip offers a significant leap in the performance for CMP intrachip communication systems delivering low-latencies and ultra-high throughputs per core while consuming minimal power