A Ghz Mos Adaptive Pipeline Technique Using Variable Delay Circuits
A Ghz Mos Adaptive Pipeline Technique Using Variable Delay Circuits
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使用可变延迟电路的 Ghz Mos 自适应流水线技术
DOI：
10.1109/vlsic.1994.586195
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
H. Yamada
中科院分区：
文献类型：
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作者：
M. Mizuno;M. Yamashina;K. Furuta;H. Igura;H. Abiko;K. Okabe;A. Ono;H. Yamada
在生产实用的GHz同步lsi时遇到两个主要障碍。首先是过度的设计余量，在试图有效地适应电路延迟和时钟倾斜的偏差时必须考虑：设计师不仅要考虑器件参数的偏差，还要考虑温度、电源电压等工作环境因素的变化。遇到的第二个主要障碍是高频lsi产生的过度功耗，因为它们的所有门都是在一个单一的频率上工作，这个频率是根据关键路径传播延迟时间确定的，在管线级中只有1 / 4的级具有最大的关键路径长度。管道各级闸的延时时间不需要相同。这种电力浪费需要消除。本文提出了一种自适应管道（APL）技术，该技术可以自动补偿时钟偏差，避免了将器件参数偏差或工作环境变化作为设计因素的必要性。此外，通过单独控制每个管道阶段的门延迟，APL技术能够消除过度的功耗。在APL技术中，MOS电流模逻辑（MCML）[1]被用于低噪声和可变延迟的基本逻辑电路。Tlie APL在这里应用于0.4pni MOS 1。wlghz G4bit双级流水线加法器。
Introduction Two major obstacles are encountered in the production of practical GHz synchronous LSIs. The first is the excessive design margin that must be considered in trying to efficiently accommodate both deviations in circuit delay and clock skew: designers must consider not only the deviation in device parameters but also tlie variation in such operating-environmental factors as temperature, supply voltage, etc. The second major obstacle encountered is excessive power dissipation produced by high frequency LSIs as a result of tlie fact that all of their gates are operated at a single frequency determined on the basis of the critical path propagation delay time in just o n e of the pipeline stages, which has the niaximum critical path length. The delay time of the gates in each pipeline stage does not need to be tlie same. This waste of power needs to be eliminated. This paper presents an adaptive pipeline (APL) teclinique which automatically compensates for clock skew and which avoids the necessity of including as design factors either device parameter deviations or operating-environment variations. Further, by individually controlling gate delay for each pipeline stage, the APL technique is able to eliminate excessive power dissipation. In the APL technique, MOS current mode logic (MCML)[l] is used for the low noise and variable delay fundamental logic circuits. Tlie APL is here applied to a 0.4pni MOS 1.W lGHz G4bit double-stage pipeline adder.