FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration
FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration
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DOI：
10.1109/socc58585.2023.10257022
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发表时间：
2023-06
期刊：
影响因子：
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通讯作者：
M. Vemuri;Umamaheswara Rao Tida
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文献类型：
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作者：
M. Vemuri;Umamaheswara Rao Tida
单片三维集成电路(M3D-IC)已经成为提高晶体管密度的一个有吸引力的选择。在M3D-IC中，基板层是使用顺序集成技术在先前层之上实现的。最近在M3D-IC中的工作已经证明了基于FDSOI工艺的M3D-IC实现的可行性，金属层间通孔(MIV)被用来提供层间器件之间的连接。由于MIV从底层延伸到顶层，因此它们占用很小的面积，从而产生面积开销。此外，需要最小间隔来促进MIV和晶体管之间的连接，这进一步增加了这一开销。为此，我们研究了MIV的替代利用，以制造具有不同沟道的MIV晶体管。我们还提出了一种使用级别70的SPICE参数来提取所提出模型的SPICE参数的策略。最后，通过一个基于标准单元的门级比较，比较了传统两层2D FDSOI晶体管实现与所提出的模型的功耗、性能和面积(PPA)指标。标准单元设计的仿真结果表明，与传统方法相比，该方法可以平均减少18%的版图面积。此外，标准电池的功耗和延迟时间平均分别降低1%和3%。
Monolithic Three-Dimensional Integrated Circuits (M3D-IC) has become an attractive option to increase the transistor density. In M3D-IC, substrate layers are realized on top of previous layers using sequential integration techniques. Recent works in M3D-IC have demonstrated the feasibility of FDSOI process-based M3D-IC implementations and, Metal inter-layer vias (MIVs) are used to provide connections between the inter-layer devices. Since MIVs are extended from bottom layer to top layer, they occupy a small area resulting in area overhead. Additionally, a minimum separation is required to facilitate connection between MIV and transistors which increases this overhead further. Towards this, we studied the alternate utilization of MIV to create MIV-transistors with varying channels. We have also presented a strategy to extract the Spice parameters of the proposed models using level 70 spice parameters. Finally, a standard cell based gate level comparison is presented to compare the Power, Performance and Area (PPA) metrics of the traditional two layer 2D FDSOI transistor implementation with the proposed models. Simulation results from standard cell designs suggest that the proposed methodology can reduce 18% layout area on average compared to the traditional approach. In addition, power consumption and delay time of the standard cells are reduced by 1% and 3% on average respectively.