Implementation of dual-direction SCR devices in analog CMOS process
Implementation of dual-direction SCR devices in analog CMOS process
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DOI：
10.1109/eosesd.2007.4401734
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发表时间：
2007-12
期刊：
影响因子：
--
通讯作者：
V. Vashchenko;V. Kuznetsov;P. Hopper
中科院分区：
文献类型：
--
作者：
V. Vashchenko;V. Kuznetsov;P. Hopper
Implementation of the dual-direction SCRs in a 5 V analog CMOS process was studied using pulsed I-V measurements and numerical simulations. A positive feedback mechanism associated with a parasitic vertical PNP was found, discussed and further utilized to improve the SCR latch-up robustness. The 2kV HBM 200V MM ESD protection capabilities with the holding voltage exceeding 5V were demonstrated in the ESD cells with the footprint size smaller than 2100 sq. um.
