Programmable Asynchronous Pipeline Arrays
Programmable Asynchronous Pipeline Arrays
复制标题
可编程异步管道阵列
DOI：
10.1007/978-3-540-45234-8_34
复制
发表时间：
2003
影响因子：
3.2
通讯作者：
R. Manohar
中科院分区：
文献类型：
--
作者：
J. Teifel;R. Manohar
我们讨论高性能的异步管道阵列（PAPAS）。定制异步设计的速度和能源益处，同时还提供了制作后的逻辑重新配置。爸爸在0.25μmCMOS工艺中的设计峰值管道吞吐量为395MHz，用于异步逻辑。
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data throughput with fine-grain pipelined asynchronous circuits. We show how the PAPA architecture maintains most of the speed and energy benefits of a custom asynchronous design, while also providing post-fabrication logic reconfigurability. We report results for a prototype PAPA design in a 0.25μm CMOS process that has a peak pipeline throughput of 395MHz for asynchronous logic.