Transaction-based debugging of system-on-chips with patterns
Transaction-based debugging of system-on-chips with patterns
复制标题
使用模式对片上系统进行基于事务的调试
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
M. Fujita
中科院分区：
文献类型：
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作者：
A. M. Gharehbaghi;M. Fujita
本文提出了一种在硅后验证中调试系统通信的方法。首先，我们在运行时使用片上电路提取事务序列，并将其存储在跟踪缓冲区中。然后，我们读取存储的交易并使用软件进行分析。分析软件试图在提取的事务中找到由我们的事务调试模式规范语言（TDPSL）定义的某些模式。我们还为TDPSL中的竞争和死锁等常见通信问题定义了一些标准模式。为了证明该方法的可行性，它被应用到一些片上总线。结果表明，该方法的面积开销非常低。我们还实现了分析软件，并表明它是内存效率，可扩展性和有效的发现错误。所提出的方法也可以应用于故障分析，包括瞬态故障。
This paper presents a debug method for system communications in post-silicon verification. First, we extract transaction sequences at run-time using on-chip circuits and store them in a trace buffer. Then, we read the stored transactions and analyze them with software. The analysis software tries to find certain patterns in the extracted transactions that are defined by our transaction debug pattern specification language (TDPSL). We have also defined a number of standard patterns for common communication problems such as race and deadlock in TDPSL. To show the feasibility of the method, it is applied to a number of on chip buses. It is shown that the area overhead of the method is very low. Also we have implemented the analysis software and shown that it is memory efficient, scalable and effective to find bugs. The proposed method can also be applied to fault analysis including transient faults.