DRAM Controller with a Close-Page Predictor
DRAM Controller with a Close-Page Predictor
复制标题
具有闭页预测器的 DRAM 控制器
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
N. Milenkovic
中科院分区：
文献类型：
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作者：
V. Stankovic;N. Milenkovic
更好地了解程序行为有助于克服中央处理器和DRAM芯片实现的主存储器的速度差异。它允许我们预测所需的下一个动作，根据观察到的主内存访问模式，这可以隐藏一些时间组件在访问DRAM内存。本文作者提出了一个简单的死区时间预测器，它有助于预测何时关闭打开的DRAM行。在本文中，该预测器进一步改进，增加了零生存时间预测器。零存活时间预测器本质上完成了死区时间预测器
Better insight of programs behavior can help in overcoming large speed difference of central processors and main memories implemented with DRAM chips. It allows us to predict required next actions, based on observed main memory access patterns, which can hide some time components in accessing DRAM memory. Authors of this paper proposed a simple dead time predictor which helps in predicting when to close the opened DRAM row. In this paper this predictor is further improved by adding a zero live time predictor. The zero live time predictor, by its essence, completes the dead time predictor