Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems

Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems
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DOI:
10.1109/hpca.2018.00037
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发表时间:
2018-02
期刊:
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)
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通讯作者:
Matheus A. Ogleari;E. Miller;Jishen Zhao
Matheus A. Ogleari;E. Miller;Jishen Zhao
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其他
文献类型:
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作者:
Matheus A. Ogleari;E. Miller;Jishen Zhao

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持久性内存是一种新的内存层,其功能是传统存储系统和主存的混合。它结合了两者的优点:存储的数据持久性和内存的快速加载/存储接口。大多数以前的持久性内存设计都对到达持久性内存的写入顺序进行了仔细的控制。这可以防止高速缓存和存储器控制器通过写入合并和重新排序来优化系统性能。我们确定,这样的写顺序控制可以放宽采用撤销+重做日志记录持久性内存系统中的数据。然而,由于性能和能量开销,传统的软件日志记录机制在持久性存储器中采用是昂贵的。以前提出的硬件日志记录方案效率低下,不能完全解决软件中的问题。为了解决这些挑战,我们提出了一个硬件撤销+重做日志计划,利用商品缓存中使用的写回,写分配策略,保持数据持久性。此外,我们开发了一个缓存强制回写机制,在硬件上显着降低的性能和能源开销,从强制数据到持久性内存。我们的持久内存微基准测试和真实的工作负载的评估表明,我们的设计显着提高了系统吞吐量,降低了动态能量和内存流量。与软件方法相比,它还提供了强大的一致性保证。
Persistent memory is a new tier of memory that functions as a hybrid of traditional storage systems and main memory. It combines the benefits of both: the data persistence of storage with the fast load/store interface of memory. Most previous persistent memory designs place careful control over the order of writes arriving at persistent memory. This can prevent caches and memory controllers from optimizing system performance through write coalescing and reordering. We identify that such write-order control can be relaxed by employing undo+redo logging for data in persistent memory systems. However, traditional software logging mechanisms are expensive to adopt in persistent memory due to performance and energy overheads. Previously proposed hardware logging schemes are inefficient and do not fully address the issues in software. To address these challenges, we propose a hardware undo+redo logging scheme which maintains data persistence by leveraging the write-back, write-allocate policies used in commodity caches. Furthermore, we develop a cache forcewrite-back mechanism in hardware to significantly reduce the performance and energy overheads from forcing data into persistent memory. Our evaluation across persistent memory microbenchmarks and real workloads demonstrates that our design significantly improves system throughput and reduces both dynamic energy and memory traffic. It also provides strong consistency guarantees compared to software approaches.