Decoding algorithms for nonbinary LDPC codes over GF(q)

Decoding algorithms for nonbinary LDPC codes over GF(q)
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DOI:
10.1109/tcomm.2007.894088
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发表时间:
2007-04-01
影响因子:
8.3
通讯作者:
Fossorier, Marc
Fossorier, Marc
中科院分区:
计算机科学2区
文献类型:
--
作者:
Declercq, David;Fossorier, Marc

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在这封信中,我们解决了在有限字段GF(Q)上解码非二进制低密度平价检查(LDPC)代码的问题,具有可理性的复杂性和良好的性能。在这封信的第一部分中,我们回想起原始的信念传播(BP)解码算法及其傅立叶域的实现。我们表明,对于算法描述和理解,将张量符号用于消息非常方便。在第二部分。信件,我们介绍了一个简化的解码器,该解码器的灵感来自二进制LDPC代码的Min-SUM解码器。我们称此解码器延长的Min-SUM(EMS)。我们表明,通过计算消息中值数量有限的近似可靠性度量,可以大大降低检查节点处理的计算复杂性。通过选择适当的校正因子或偏移,我们表明EMS解码器性能相当不错,在某些情况下,比常规BP解码器更好。通过模拟密度演化,渐近地获得了因子和偏移校正的最佳值。我们对非常高的阶段的Ultra-Sparse代码进行的模拟表明,非二进制LDPC代码对于需要小或中等密码字的帧速率率的应用有望。 EMS解码器是对此类代码实践实施的实用硬件实现的好候选者。
In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonnable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the. letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computationnal complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes.