Threshold network synthesis and optimization and its application to nanotechnologies
Threshold network synthesis and optimization and its application to nanotechnologies
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DOI：
10.1109/tcad.2004.839468
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发表时间：
2005
影响因子：
2.9
通讯作者：
Rui Zhang;Pallav Gupta;Lin Zhong;N. Jha
中科院分区：
文献类型：
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作者：
Rui Zhang;Pallav Gupta;Lin Zhong;N. Jha
提出了一种基于任意多输出布尔函数的有效阈值网络合成算法。许多纳米技术，如共振隧道二极管、量子元胞自动机和单电子隧道，都能够有效地实现阈值逻辑。这项工作的主要目的是弥合目前纳米级器件研究与利用这些器件生成优化网络的综合方法研究之间的巨大差距。虽然基于纳米技术的功能正确的阈值门和电路已经成功展示，但目前还没有通用的多电平阈值网络合成的方法或设计自动化工具。我们已经建立了第一个这样的工具，阈值逻辑合成器（TELS），在现有的布尔逻辑合成工具之上。56个多输出基准的实验表明，与传统的逻辑合成相比，门数和互连数分别减少80.0%和70.6%，平均分别为22.7%和12.6%。此外，合成的网络具有良好的结构平衡性。这项工作的新颖之处在于引入了第一个用于通用多电平阈值逻辑设计的综合综合方法和工具。
We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. Many nanotechnologies, such as resonant tunneling diodes, quantum cellular automata, and single electron tunneling, are capable of implementing threshold logic efficiently. The main purpose of this work is to bridge the current wide gap between research on nanoscale devices and research on synthesis methodologies for generating optimized networks utilizing these devices. While functionally-correct threshold gates and circuits based on nanotechnologies have been successfully demonstrated, there exists no methodology or design automation tool for general multilevel threshold network synthesis. We have built the first such tool, threshold logic synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with 56 multioutput benchmarks indicate that, compared to traditional logic synthesis, up to 80.0% and 70.6% reduction in gate count and interconnect count, respectively, is possible with the average being 22.7% and 12.6%, respectively. Furthermore, the synthesized networks are well-balanced structurally. The novelty of this work lies in the introduction of the first comprehensive synthesis methodology and tool for general multilevel threshold logic design.