High level synthesis of stereo matching: Productivity, performance, and software constraints
High level synthesis of stereo matching: Productivity, performance, and software constraints
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立体匹配的高级综合：生产力、性能和软件限制
DOI：
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发表时间：
2011
期刊：
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通讯作者：
Deming Chen
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文献类型：
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作者：
K. Rupnow;Yun Liang;Yinan Li;Dongbo Min;M. Do;Deming Chen
对于具有高计算需求和低能耗要求的应用来说，FPGA 是一个极具吸引力的平台。然而，FPGA 实现的设计工作量仍然很高，通常比使用高级语言的设计工作量大一个数量级。高级综合 (HLS) 工具可以从 C/C++/SystemC 等高级语言 (HLL) 生成硬件实现，而不是这种耗时的过程。此类工具减少了设计工作：高级描述更加紧凑且不易出错。 HLS 工具承诺从软件设计人员对实施平台的了解中抽象出硬件开发。在本文中，我们研究了立体匹配的几种实现方式，立体匹配是计算机视觉研究的一个活跃领域，它使用图像去噪、图像检索、特征匹配和人脸识别中常见的技术。我们对使用 HLS 对典型立体匹配软件的适用性、AutoPilot（最先进的 HLS 工具）的可用性和生产力以及 AutoPilot 生成的设计的性能进行了公正的评估。根据我们的研究，我们提供了软件设计指南、使用 HLS 将通用软件映射到硬件的局限性以及 HLS 工具开发的未来方向。对于立体匹配算法，我们证明了软件速度提高了 3.5 倍到 67.9 倍（但低于手动 RTL 设计可实现的速度），与手动硬件设计相比，设计工作量减少了五倍。
FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high — often an order of magnitude larger than design effort using high level languages. Instead of this time-consuming process, high level synthesis (HLS) tools generate hardware implementations from high level languages (HLL) such as C/C++/SystemC. Such tools reduce design effort: high level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we examine several implementations of stereo matching, an active area of computer vision research that uses techniques also common for image de-noising, image retrieval, feature matching and face recognition. We present an unbiased evaluation of the suitability of using HLS for typical stereo matching software, usability and productivity of AutoPilot (a state of the art HLS tool), and the performance of designs produced by AutoPilot. Based on our study, we provide guidelines for software design, limitations of mapping general purpose software to hardware using HLS, and future directions for HLS tool development. For the stereo matching algorithms, we demonstrate between 3.5X and 67.9X speedup over software (but less than achievable by manual RTL design) with a five-fold reduction in design effort vs. manual hardware design.