Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation
Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation
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DOI：
10.1109/tcsii.2008.923411
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发表时间：
2008-09-01
影响因子：
4.4
通讯作者：
Jung, Seong-Ook
中科院分区：
文献类型：
--
作者：
Nho, Hyunwoo;Yoon, Sei-Seung;Jung, Seong-Ook
本文描述了一种数值计算亚100 nm SRAM的设计裕度和估计与读访问失败相关的成品率的方法。低于100 nm的工艺变化不仅影响SRAM单元，还影响外围电路，如读出放大器(SA)和跟踪方案。同时包含SRAM单元和周围电路的模拟要么精确，但计算代价高昂(全面的蒙特卡罗模拟)，要么过于简单(固定拐角设计)，无法捕捉关键的统计变化问题，这在100 nm以下的设计中占主导地位。通过数学结合SRAM单元和每个外围模块的蒙特卡罗模拟结果，我们表明，在固定角点模拟低估19%的情况下，SA输入电压的分布可以被准确地估计。结合SA输入电压和SA偏移量分布给出了成品率方程，可用于设计点的选择。此外，从产量数据导出了产量灵敏度，以确保产量与设计变量具有良好的相关性。
This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.