Cycle-accurate modeling of multicore processors on FPGAs

Cycle-accurate modeling of multicore processors on FPGAs
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FPGA 上多核处理器的周期精确建模

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发表时间:
2013
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通讯作者:
Asif Khan
Asif Khan
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作者:
Asif Khan

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我们提出了一种新的建模方法,使生成一个高性能,周期准确的模拟器从目标设计的周期级规格。我们描述Arete,一个全系统的多核处理器模拟器,使用我们的建模方法开发。我们提供的细节Arete的资源效率和高性能的实现在多个FPGA平台上,并使用它进行的架构实验。我们提出了明确的证据表明,在架构研究中使用简化模型可能会导致错误的结论。通过使用cycleaccurate模型和简化模型进行的两个实验,我们表明,一方面,结果存在大量的定量和定性差异,另一方面,结果匹配得很好。论文导师:Arvind职称:电气工程与计算机科学约翰逊教授
We present a novel modeling methodology which enables the generation of a highperformance, cycle-accurate simulator from a cycle-level specification of the target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on Arete's resource-efficient and high-performance implementation on multiple FPGA platforms, and the architectural experiments performed using it. We present clear evidence that the use of simplified models in architectural studies can lead to wrong conclusions. Through two experiments performed using both cycleaccurate and simplified models, we show that on one hand there are substantial quantitative and qualitative differences in results, and on the other, the results match quite well. Thesis Supervisor: Arvind Title: Johnson Professor of Electrical Engineering and Computer Science
DOI: --
发表时间: 2004
期刊: 第22回日本ロボット学会学術講演会予稿集
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作者:
M.Higashimori;東森 充;東森 充
通讯作者: 東森 充