A Low-Power DCO Using Interlaced Hysteresis Delay Cells
A Low-Power DCO Using Interlaced Hysteresis Delay Cells
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DOI：
10.1109/tcsii.2012.2213357
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发表时间：
2012-10-01
影响因子：
4.4
通讯作者：
Lee, Chen-Yi
中科院分区：
文献类型：
--
作者：
Yu, Chien-Ying;Chung, Ching-Che;Lee, Chen-Yi
本文介绍了一种低功耗小面积数字控制振荡器(DCO)。采用二进制加权延迟级的粗细结构对延时范围和分辨率进行了优化。与传统的延迟单元相比，DCO的粗调谐级使用隔行滞后延迟单元，其功率和面积效率更高。毛刺保护同步电路使DCO易于控制，不会产生毛刺。采用90 nm工艺制作了一个全数字锁相环，有效面积为0.0086 mm(2)。在1V电源下测量的输出频率范围为180~530 MHz，在480 MHz和200 MHz输出时的功耗分别为466和357微瓦。
This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm(2). The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 mu W at 480- and 200-MHz output, respectively.