PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM
PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM
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DOI：
10.1109/dsn.2016.30
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发表时间：
2016-06
期刊：
影响因子：
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通讯作者：
S. Khan;Donghyuk Lee;O. Mutlu
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文献类型：
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作者：
S. Khan;Donghyuk Lee;O. Mutlu
系统级检测和缓解DRAM故障提供了各种系统增强功能，例如更好的可靠性、可扩展性、能量和性能。不幸的是，系统级检测对于依赖于相邻单元的数据内容的DRAM故障(数据相关故障)是具有挑战性的。DRAM供应商在内部扰乱/重新映射系统级地址空间。因此，使用相邻系统级地址测试数据相关故障实际上并不测试物理上相邻的单元。在这项工作中，我们认为发现系统中数据相关故障的一个有希望的方法是确定系统地址空间中物理相邻单元的位置。不幸的是，如果做得很天真，这样的测试即使在单个内存行中也需要49天来检测相邻地址，这在实际系统中是不可行的。我们开发了PARBOR，这是一种高效的系统级技术，它确定物理上相邻的DRAM单元在系统地址空间中的位置，并使用该信息来检测与数据相关的故障。据我们所知，这是第一个解决在存在DRAM的情况下检测DRAM中的数据相关故障的挑战的工作-系统级地址的内部加扰。我们使用三家主要厂商的144块实际DRAM芯片，通过实验验证了PARBOR的有效性。我们的实验评估表明，PARBOR 1)只需66-90次测试即可检测相邻小区位置，与朴素测试相比减少了745,654倍；2)与不知道相邻小区位置的随机模式测试相比，PARBOR发现的失败次数多21.9%。我们引入了一种新的机制，该机制利用PARBOR根据存储单元的数据内容来降低刷新率，从而提高了系统的性能和效率。我们希望我们的快速高效的系统级检测技术能够支持其他新的想法和机制，以提高基于DRAM的存储系统的可靠性、性能和能效。
System-level detection and mitigation of DRAM failures offer a variety of system enhancements, such as better reliability, scalability, energy, and performance. Unfortunately, system-level detection is challenging for DRAM failures that depend on the data content of neighboring cells (data-dependent failures). DRAM vendors internally scramble/remap the system-level address space. Therefore, testing data-dependent failures using neighboring system-level addresses does not actually test the cells that are physically adjacent. In this work, we argue that one promising way to uncover data-dependent failures in the system is to determine the location of physically neighboring cells in the system address space. Unfortunately, if done naively, such a test takes 49 days to detect neighboring addresses even in a single memory row, making it infeasible in real systems. We develop PARBOR, an efficient system-level technique that determines the locations of the physically neighboring DRAM cells in the system address space and uses this information to detect data-dependent failures. To our knowledge, this is the first work that solves the challenge of detecting data-dependent failures in DRAM in the presence of DRAM-internal scrambling of system-level addresses. We experimentally demonstrate the effectiveness of PARBOR using 144 real DRAM chips from three major vendors. Our experimental evaluation shows that PARBOR 1) detects neighboring cell locations with only 66-90 tests, a 745,654X reduction compared to the naive test, and 2) uncovers 21.9% more failures compared to a random-pattern test that is unaware of the neighbor cell locations. We introduce a new mechanism that utilizes PARBOR to reduce refresh rate based on the data content of memory locations, thereby improving system performance and efficiency. We hope that our fast and efficient system-level detection technique enables other new ideas and mechanisms that improve the reliability, performance, and energy efficiency of DRAM-based memory systems.