Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads
Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads
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DOI：
10.1016/j.future.2022.05.023
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发表时间：
2022-06
期刊：
影响因子：
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通讯作者：
Dhruv Gajaria;Tosiron Adegbija
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文献类型：
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作者：
Dhruv Gajaria;Tosiron Adegbija
近年来，可穿戴设备在消费者和工业应用中的普及度呈指数级增长。尽管这些设备受到严格的面积和能源限制，但它们正在处理日益复杂和数据丰富的工作负载，因此需要创新的面积和能源高效的计算解决方案和架构。本文探讨自旋转移矩RAM（STT-RAM）作为设计面积和能源效率的可穿戴处理器缓存的候选。首先，我们分析了16个真实可穿戴工作负载的内存占用，并将其与SPEC 2017和MiBench等通用基准进行比较。然后，我们分析了可穿戴工作负载的内存特性，揭示了可穿戴工作负载是高度读密集型的，这使得它们比通用工作负载更不容易受到STT-RAM缓存中固有的写入延迟/能量开销的影响。我们的分析还表明，可穿戴工作负载具有较低的缓存可变性需求，其缓存块具有较短且稳定的寿命。在此分析的背景下，我们探讨了可穿戴工作负载的STT-RAM缓存架构设计的权衡。具体来说，我们探索一个简单的适应性设计，旨在优化延迟或能源，基于运行时的需求，而不引入显着的设计或面积开销。我们的分析表明，STT-RAM缓存提供了能源和面积高效的可穿戴计算的承诺，而不会引入太多的性能开销。
Wearable devices have grown exponentially in popularity in both consumer and industrial applications in recent years. Despite their stringent area and energy constraints, these devices are processing increasingly complex and data-rich workloads, necessitating innovative area- and energy-efficient computing solutions and architectures. This paper explores spin-transfer torque RAM (STT-RAM) as a candidate for designing area- and energy-efficient wearable processor caches. First, we analyze the memory footprints of 16 real-world wearable workloads and compare them to general-purpose benchmarks like SPEC 2017 and MiBench. Then, we analyze the wearable workloads’ memory characteristics to reveal that wearable workloads are highly read-intensive, making them less vulnerable than general-purpose workloads to the write latency/energy overheads inherent in STT-RAM caches. Our analysis also reveals that wearable workloads have low cache variability needs, and their cache blocks exhibit short and stable lifetimes. Against the background of this analysis, we explore the tradeoffs of STT-RAM cache architecture designs for the wearable workloads. Specifically, we explore a simple adaptable design that aims to optimize latency or energy, based on runtime needs, without introducing significant design or area overhead. Our analysis shows that STT-RAM caches offer much promise for energy- and area-efficient wearable computing, without introducing much performance overheads.