A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors
A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors
复制标题
用于 CMOS 图像传感器的低功耗列并行增益自适应单斜率 ADC
DOI：
10.3390/electronics9050757
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发表时间：
2020-05-01
期刊：
影响因子：
2.9
通讯作者：
Li, Dongmei
中科院分区：
文献类型：
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作者：
Wei, Jingwei;Li, Xuan;Li, Dongmei
提出了一种用于CMOS图像传感器的低功耗列并行增益自适应单斜率模数转换器。所提出的基于开关电容的增益控制结构实现了增益自适应功能，与传统的单斜率ADC相比只需要很小的改变。为了降低列电路的功耗，提出了一种开关电容控制的动态偏置比较器和一个反转减缩的上下双倍数据速率(DDR)计数器。在斜坡发生器中，采用了一种具有二维梯度容错开关的12位电流舵型数模转换器(DAC)来改善ADC的线性度。所提出的技术在采用台积电180 nm工艺制造的原型芯片上得到了实验验证。单列A/D转换器的功耗为63.2μW，面积为4.48μm×310μm，其微分非线性系数和积分非线性系数分别为−0.43/+0.46和−0.84/+1.95LSB。校准后，在满刻度的0.08%范围内，获得了13位的线性输出。
A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 μ W and occupies an area of 4.48 μ m × 310 μ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration.