A 0.33–1 GHz Open-Loop Duty Cycle Corrector With Digital Falling Edge Modulator
A 0.33–1 GHz Open-Loop Duty Cycle Corrector With Digital Falling Edge Modulator
复制标题
具有数字下降沿调制器的 0.33–1 GHz 开环占空比校正器
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Kangyoon Lee
中科院分区：
文献类型：
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作者：
Kyung;Sang;Sung Jin Kim;Dongsoo Lee;Sang;Kangyoon Lee
本简介介绍了带有数字下降沿调制器的开环占空比校正器 (DCC)。所提出的 DCC 由用于边缘对齐的环路延迟链和用于增强相位插值限制的下降沿调制器组成。除了低频外，这些功能还提高了高频下的占空比偏移校正范围，具有快速锁定时间，并且不会降低相位内插器连接点的信号完整性。所提出的 DCC 采用 TSMC 55 nm CMOS 技术制造，电源电压为 1 V，面积为 0.0186 mm2。实测结果表明，在1 GHz时，当输入时钟的占空比从80%变为20%时，输出时钟的占空比误差调整至小于2%，并且锁定周期仅消耗5个周期。在 1 GHz 时，功耗为 2.09 mW，峰峰值抖动为 12.53 ps。
This brief presents an open-loop duty cycle corrector (DCC) with digital falling edge modulator. The proposed DCC consists of a loop delay chain for edge alignment and a falling edge modulator to enhance the phase interpolating limit. These features improved the duty offset correction range at high frequency besides low frequency with fast lock time and without degrading the signal integrity of the junction of a phase interpolator. The proposed DCC was fabricated in a TSMC 55-nm CMOS technology with 1-V supply voltage and the area occupied 0.0186 mm2. The measured results show that the duty cycle error of the output clock was adjusted to less than 2% when the duty cycle ratio of the input clock was changed from 80% to 20% at 1 GHz, and the lock cycle consumed only five cycles. At 1 GHz, the power consumption was 2.09 mW and the peak-to-peak jitter was measured at 12.53 ps.