Scalable Resonant Power Clock Generation for Adiabatic Logic Design
Scalable Resonant Power Clock Generation for Adiabatic Logic Design
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DOI：
10.1109/isvlsi51109.2021.00068
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发表时间：
2021-07
期刊：
影响因子：
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通讯作者：
Ragh Kuttappa;Leo Filippini;Nicholas Sica;B. Taskin
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文献类型：
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作者：
Ragh Kuttappa;Leo Filippini;Nicholas Sica;B. Taskin
在本文中，提出了一种用于绝热逻辑电路（包括绝热核心）的可扩展且无源无元件功率时钟生成。电源时钟传统上是正弦信号，充当绝热门的电源和定时源。功率时钟信号的斜率直接影响绝热门的整体能量效率。先前的工作已考虑使用基于 LC 的电源时钟生成电路，由于面积和高 Q 电感器要求，这种电路通常被认为成本高昂。本文提出了一种可扩展的解决方案，其特点是采用谐振时钟设计的步进充电电路中的电源时钟生成电路具有独特的创新。特别是，谐振旋转式时钟用于为步进充电电源时钟电路提供低功率控制。基于 SPICE 的仿真在 LGSynth’91 基准电路的大规模绝热实现上以 400 MHz 进行。所提出的实现的整体能效与采用传统 LC 电源时钟解决方案的等效绝热电路的整体能效进行了比较。
In this paper, a scalable and passive component-less power-clock generation for adiabatic logic circuits, inclusive of the adiabatic core, is presented. The power-clock is traditionally a sinusoidal signal, that acts as the power and timing source to adiabatic gates. The slope of the power-clock signal directly impacts the overall energy efficiency of the adiabatic gates. Prior works have considered using LC based power-clock generation circuits, which are often considered costly due to area and high-Q inductor requirements. In this paper, a scalable solution is presented that features a unique innovation for the power clock generation circuit in step-charged circuits designed with resonant clocking. In particular, resonant rotary style clocking is used to provide the low power control to step-charged power clock circuits. SPICE based simulations are performed at 400 MHz on large scale adiabatic implementations of LGSynth’91 benchmark circuits. The overall energy efficiency of the proposed implementations are compared to those of equivalent adiabatic circuits with a traditional LC power-clock solution.