A 90-nm Low-Power FPGA for Battery-Powered Applications
A 90-nm Low-Power FPGA for Battery-Powered Applications
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DOI：
10.1145/1117201.1117203
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发表时间：
2006-02
影响因子：
2.9
通讯作者：
Tim Tuan;Arifur Rahman;Satyaki Das;S. Trimberger;S. Kao
中科院分区：
文献类型：
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作者：
Tim Tuan;Arifur Rahman;Satyaki Das;S. Trimberger;S. Kao
现场可编程门阵列(现场可编程门阵列)等可编程逻辑器件可用于广泛的应用。然而，现场可编程门阵列并不常用于电池供电的应用中，因为它们比应用指定的集成电路消耗更多的功率，并且缺乏电源管理功能。在本文中，我们描述了一种面向电池供电应用的低功耗FPGA内核PICA的设计与实现。我们的设计基于商用低成本的现场可编程门阵列，通过一系列的功耗优化实现了可观的功耗节约。由此产生的体系结构与现有的商业设计工具兼容。该实现是在90 nm三层氧化物CMOS工艺中完成的。与基准设计相比，PICA的主用功率降低了46%，备用功率降低了99%。此外，它在待机模式期间保持电路和配置状态，并在大约100 ns内从待机模式唤醒
Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns