Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection
Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection
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DOI：
10.1145/3225058.3225104
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发表时间：
2018-08
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通讯作者：
Xian Zhu;R. Wernsman;Joseph Zambreno
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作者：
Xian Zhu;R. Wernsman;Joseph Zambreno
现代图形处理单元 (GPU) 利用 L1 数据 (L1D) 缓存来降低内存带宽要求和延迟。然而，L1D 缓存很容易被 GPU 功能单元的大量内存请求淹没，从而成为 GPU 性能的瓶颈。事实证明，对于许多 GPU 应用程序来说，L1D 缓存的性能会大大降低，因为大量 L1D 缓存行在重新引用之前就被替换了。通过检查这些应用程序的缓存访问模式，我们观察到低关联性的 L1D 缓存很难捕获具有不同重用模式的 GPU 应用程序的数据局部性。这些模式导致频繁的线路更换和低数据重用。为了提高L1D缓存的效率，我们设计了动态行保护方案（DLP），它既可以保留有价值的缓存行，又可以提高缓存行利用率。 DLP 从 L1D 缓存收集数据重用信息。该信息用于预测运行时每个内存指令的保护距离，这有助于在数据局部性的利用和具有长重用距离的缓存线的过度保护之间保持平衡。当一组中的所有高速缓存行都受到保护时，冗余高速缓存未命中将被绕过，以减少对该组的争用。评估结果表明，我们提出的解决方案提高了缓存命中率，同时减少了缓存不足的应用程序的缓存流量，与基线相比，IPC 提升高达 137%，平均提升 43%。
A modern Graphics Processing Unit (GPU) utilizes L1 Data (L1D) caches to reduce memory bandwidth requirements and latencies. However, the L1D cache can easily be overwhelmed by many memory requests from GPU function units, which can bottleneck GPU performance. It has been shown that the performance of L1D caches is greatly reduced for many GPU applications as a large amount of L1D cache lines are replaced before they are re-referenced. By examining the cache access patterns of these applications, we observe L1D caches with low associativity have difficulty capturing data locality for GPU applications with diverse reuse patterns. These patterns result in frequent line replacements and low data re-usage. To improve the efficiency of L1D caches, we design a Dynamic Line Protection scheme (DLP) that can both preserve valuable cache lines and increase cache line utilization. DLP collects data reuse information from the L1D cache. This information is used to predict protection distances for each memory instruction at runtime, which helps maintain a balance between exploitation of data locality and over-protection of cache lines with long reuse distances. When all cache lines are protected in a set, redundant cache misses are bypassed to reduce the contention for the set. The evaluation result shows that our proposed solution improves cache hits while reducing cache traffic for cache-insufficient applications, achieving up to 137% and an average of 43% IPC improvement over the baseline.