Exploiting regularity for low-power design
Exploiting regularity for low-power design
复制标题
利用低功耗设计的规律性
DOI：
10.1109/iccad.1996.569540
复制
发表时间：
1996
期刊：
影响因子：
--
通讯作者：
J. Rabaey
中科院分区：
文献类型：
--
作者：
Renu Mehra;J. Rabaey
当今的行为合成技术产生的架构是互连的功率效率低。实验已经证明，在综合设计中，总功率的大约10%到40%可能被耗散在总线、多路复用器和驱动器中。我们提出了一种新的方法，针对降低功耗的互连元件总线，多路复用器和缓冲器。本文提出的调度，分配和分配技术利用算法中的规律性和常见的计算模式，以减少扇出和扇入的互连线，从而减少总线电容和简化的互连结构。平均节省47%和49%的总线和多路复用器，分别展示了一组基准的例子。
Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements-buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the regularity and common computational patterns in the algorithm to reduce the fan-outs and fan-ins of the interconnect wires, resulting in reduced bus capacitances and a simplified interconnect structure. Average power savings of 47% and 49% in buses and multiplexors, respectively, are demonstrated on a set of benchmark examples.