System energy minimization via joint optimization of the DC-DC converter and the core
System energy minimization via joint optimization of the DC-DC converter and the core
复制标题
通过 DC-DC 转换器和核心的联合优化实现系统能耗最小化
DOI：
10.1109/islped.2011.5993614
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
P. Krein
中科院分区：
文献类型：
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作者：
R. Abdallah;P. Shenoy;Naresh R Shanbhag;P. Krein
本文讨论了设计节能的嵌入式系统的问题，通过联合优化DC-DC转换器和计算核心的功耗。过去的工作表明，存在一个最小的能量工作点（MEOP）在亚阈值区域的计算核心（C-MEOP），在动态和泄漏功率平衡。MEOP由最佳能耗E、最佳电压V和最佳频率f组成的3元组定义。首先，我们表明，在动态电压缩放（DVS）的DC-DC转换器的损失导致整个系统的MEOP（S-MEOP）显着不同的C-MEOP。在一个130 nm，1.2V的商业CMOS工艺的模拟表明，在S-MEOP的工作结果在45.5%的能源节省比工作在核心电压V的C-MEOP建议。DC-DC转换器效率也提高了2.2倍。其次，我们表明，架构技术，如并行化导致的S-MEOP接近C-MEOP。因此，跟踪C-MEOP（一项更容易的片上任务）足以说明工艺变化。我们发现，DC-DC变换器的损耗降低亚阈值区，但增加在超阈值区时，采用并行化。这一观察结果使我们提出了一种可重新配置的核心架构，该架构在C-MEOP下将转换器效率提高了2.3倍，并使S-MEOP和C-MEOP的能耗在彼此的4%以内，同时将亚阈值区域的吞吐量提高了至少8倍。最后，我们表明，流水线，这已被提出，以减少核心能量在C-MEOP，同时提高吞吐量[1]，产生不利影响的S-MEOP。在S-MEOP处的流水线内核系统能量比在C-MEOP电压V_DC下操作时的流水线内核系统能量低85%。
This paper addresses the problem of designing energy-efficient embedded systems by jointly optimizing the power consumption of both the DC-DC converter and the computational core. Past work has shown that there exists a minimum energy operating point (MEOP) in the subthreshold region for computational cores (C-MEOP), at which the dynamic and leakage powers are balanced. The MEOP is defined by the 3-tuple consisting of the optimum energy consumption E∗, optimum voltage V∗ and optimum frequency f∗. First, we show that the DC-DC converter losses in dynamic voltage scaling (DVS) cause the overall system MEOP (S-MEOP) to differ significantly from C-MEOP. Simulations in a 130-nm, 1.2V commercial CMOS process show that operation at S-MEOP results in a 45.5% energy savings over operating at a core voltage V∗C suggested by C-MEOP. The DC-DC converter efficiency is also improved by 2.2X. Second, we show that architectural techniques such as parallelization cause the S-MEOP to approach C-MEOP. Thus, it is sufficient to track C-MEOP — a much easier task on-chip — in order to account for process variations. We show that DC-DC converter losses reduces in subthreshold region but increases in superthreshold region when parallelization is employed. This observation leads us to propose a reconfigurable core architecture that improves the converter efficiency by 2.3X at C-MEOP, and makes energy consumption at S-MEOP and C-MEOP to be within 4% of each other, while improving throughput in the subthreshold region by at least 8X. Finally, we show that pipelining, which has been proposed to decrease core energy at C-MEOP while improving throughput [1], adversely affects the S-MEOP. The pipelined-core system energy at S-MEOP is 85% lower than the pipelined-core system energy when operating at the C-MEOP voltage V∗C.