TITAC-2: an asynchronous 32-bit microprocessor
TITAC-2: an asynchronous 32-bit microprocessor
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TITAC-2:异步 32 位微处理器
DOI:
10.1109/aspdac.1998.669480
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发表时间:
1998
期刊:
影响因子:
--
通讯作者:
T. Nanya
中科院分区:
文献类型:
--
作者:
A. Takamura;M. Ozawa;Izumi Fukasaku;T. Fujii;Y. Ueno;Masashi Imai;M. Kuwako;T. Nanya
With the wire-delay problem moving into dominance in VLSI chip design, a fundamental limitation is being revealed in performance and dependability of synchronous systems which require global clock distribution with as little skew as possible. The worst-case delay is influenced not only by design and fabrication process but also by the operating environment, e.g. the power supply voltage and temperature. Asynchronous systems, with no global clock, can intrinsically enjoy: 1) average case performance instead of worst-case performance, 2) low power consumption, 3) ease of modular design, and 4) timing fault tolerance. We have designed and implemented a 32-bit fully asynchronous microprocessor, TITAC-2, which is the fastest and largest CMOS asynchronous microprocessor that has ever been operational.