Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT

Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT
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适用于加密分组密码 LED 和 HIGHT 的可靠硬件架构

DOI:
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发表时间:
2017
影响因子:
2.9
通讯作者:
Mehrdad Nojoumian
Mehrdad Nojoumian
中科院分区:
计算机科学3区
文献类型:
--
作者:
S. Subramanian;Mehran Mozaffari;R. Azarderakhsh;Mehrdad Nojoumian

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加密体系结构为敏感使用模型提供了不同的安全属性。但是,除非保证架构的可靠性,否则可以通过自然或恶意缺陷来破坏此类安全性。在本文中,考虑了可以在身份验证的加密算法中使用的两个基本块密码,即光加密设备,高安全性和轻质块密码。前者是高级加密标准类型的,已被认为是面积效率,而后者构成了Feistel网络结构,适用于低复杂性和低功率嵌入式安全应用程序。在本文中,我们提出了有效的误差检测架构,包括使用编码操作数和基于签名的方案重新计算的变体,以检测瞬态和永久性故障。认证的加密应用于密码学中,以同时提供与通信渠道中发送的消息同时提供机密性,完整性和真实性。在本文中,我们表明所提出的方案适用于简单轻巧CFB的案例研究,用于提供经过认证的加密和相关数据。使用Xilinx综合合成环境工具进行了误差模拟,并对Xilinx FPGA家族VirTex-7进行了基准测试,以评估所提出的架构的可靠性能力和效率。
Cryptographic architectures provide different security properties to sensitive usage models. However, unless reliability of architectures is guaranteed, such security properties can be undermined through natural or malicious faults. In this paper, two underlying block ciphers which can be used in authenticated encryption algorithms are considered, i.e., light encryption device and high security and lightweight block ciphers. The former is of the Advanced Encryption Standard type and has been considered area-efficient, while the latter constitutes a Feistel network structure and is suitable for low-complexity and low-power embedded security applications. In this paper, we propose efficient error detection architectures including variants of recomputing with encoded operands and signature-based schemes to detect both transient and permanent faults. Authenticated encryption is applied in cryptography to provide confidentiality, integrity, and authenticity simultaneously to the message sent in a communication channel. In this paper, we show that the proposed schemes are applicable to the case study of simple lightweight CFB for providing authenticated encryption with associated data. The error simulations are performed using Xilinx Integrated Synthesis Environment tool and the results are benchmarked for the Xilinx FPGA family Virtex-7 to assess the reliability capability and efficiency of the proposed architectures.