Universal test generation using fault tuples
Universal test generation using fault tuples
复制标题
使用故障元组生成通用测试
DOI：
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发表时间：
2000
期刊：
影响因子：
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通讯作者：
R. D. Blanton
中科院分区：
文献类型：
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作者：
R. Desineni;K. N. Dwarakanath;R. D. Blanton
基于故障元组的概念，开发了一种用于组合电路的测试生成工具FATGEN。FATGEN可用于同时生成对数字系统中发生的许多类型的不当行为的测试。ISCAS85基准电路中涉及SSL、晶体管卡开、路径延迟和桥接故障的单独实验表明，当同时分析所有类型的故障时，平均加速速度接近32%，测试集压缩率为60%。此外，中止故障的数量平均减少了约34%。
A test generation tool for combinational circuits called FATGEN has been developed based on the notion of fault tuples. FATGEN can be used to simultaneously generate tests for many types of misbehavior that occur in digital systems. Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup of nearly 32% and test set compaction of 60% when faults of all types are analyzed simultaneously. In addition, there is an average reduction of approximately 34% in the number of aborted faults.