A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications
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DOI：
10.1109/jssc.2003.813248
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发表时间：
2003-07
期刊：
影响因子：
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通讯作者：
T. Enomoto;Yoshinori Oka;H. Shikano
中科院分区：
文献类型：
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作者：
T. Enomoto;Yoshinori Oka;H. Shikano
研制了一种电压电平自控制电路，该电路可根据需要向有源负载电路提供最大直流电压，也可在待机状态下降低提供给负载电路的直流电压。这种SVL电路可以大大降低CMOS逻辑电路的待机泄漏功率，在芯片面积和速度方面的开销最小。此外，它也可以应用于存储器和寄存器，因为这种电路配备了SVL电路可以保持数据，即使在待机模式。具有片上SVL电路的8位0.13-/spl μ/m CMOS涟漪进位加法器（RCA）的待机功率为8.2 nW，即，等效常规加法器的待机功率的4.0%，而输出信号延迟为786 ps，即，仅比等效常规加法器的输出信号延迟长2.3%。此外，对于0.13 μ/m512位SRAM，包含SVL电路的512位存储单元阵列的待机功率为69.1nW，这是等效的传统存储单元阵列的待机功率的3.9%。该0.13-/spl mu/m SRAM的读访问时间为285 ps，即仅比等效SRAM慢2 ps。
A self-controllable voltage level (SVL) circuit which can supply a maximum dc voltage to an active-load circuit on request or can decrease the dc voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-/spl mu/m CMOS ripple carry adder (RCA) with an on-chip SVL circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-/spl mu/m 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-/spl mu/m SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.