At-speed built-in test for logic circuits with multiple clocks
At-speed built-in test for logic circuits with multiple clocks
复制标题
具有多个时钟的逻辑电路的全速内置测试
DOI：
10.1109/ats.2002.1181726
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发表时间：
2002
期刊：
影响因子：
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通讯作者：
Yasuo Sato
中科院分区：
文献类型：
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作者：
K. Hatayama;M. Nakao;Yasuo Sato
本文提出了一种多时钟逻辑电路的全速内建测试方法。显然，内建自测试（BIST）在SoC的测试策略中起着关键的作用。很明显，高速内建自测试对于高质量的测试是必要的。虽然有几种方法可以实现全速BIST，但仍然存在一些问题，如多时钟，多周期传输和错误路径。该方法利用LFSR重播种技术，在合理的测试时间内实现了对任意释放和捕获时钟组合的全速测试。基准电路和工业电路的实验结果表明，我们的方法的有效性。
This paper presents an at-speed built-in test method for logic circuits with multiple clocks. It is clear that BIST (built-in self-test) plays a key role in test strategy for SoCs. It is also obvious that at-speed BIST is necessary for high quality test. Though several approaches enable at-speed BIST, there still exist several issues, such as multiple clocks, multi-cycle transfers and false paths. The proposed method realizes at-speed test for arbitrary combination of release and capture clocks at reasonable test time by utilizing the LFSR reseeding technique. Experimental results for benchmark circuits and an industrial circuit are given to illustrate the effectiveness of our approach.