Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
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DOI：
10.1587/transfun.e93.a.2472
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发表时间：
2010-12
期刊：
影响因子：
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通讯作者：
Xin Man;T. Horiyama;S. Kimura
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文献类型：
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作者：
Xin Man;T. Horiyama;S. Kimura
时钟门控是在不违背原设计功能正确性的前提下，为寄存器插入控制信号，选择性地关闭不必要的时钟信号，从而降低动态功耗。商业EDA工具通常具有基于结构方法生成时钟门控逻辑的机制，其中使用设计者指定的控制信号，时钟门控的有效性取决于指定的控制信号。在研究中，我们重点研究了自动时钟门控逻辑的生成，提出了一种基于候选信号提取和控制信号选择的方法。利用线性公式形式化控制信号的选择，设计了一种基于BDD的优化方法。该方法对于不同寄存器有大量共享候选者的电路是有效的。将该方法应用于反电路，验证了与功率仿真结果和一组基准电路的相关性。在布局后，反向电路的功耗降低了19.1-71.9%，基准电路的成本降低了2.3-18.0%。
Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.