A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs
A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs
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DOI：
10.1109/ipdps.2004.1303134
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发表时间：
2004-04
期刊：
影响因子：
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通讯作者：
G. Govindu;S. Choi;V. Prasanna;V. Daga;Sridhar Gangadharpalli;V. Sridhar
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文献类型：
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作者：
G. Govindu;S. Choi;V. Prasanna;V. Daga;Sridhar Gangadharpalli;V. Sridhar
仅提供摘要形式。我们首先开发了一种新的架构，用于流输入矩阵的定点LU分解，在FPGA上。我们的架构，基于一个圆形的线性阵列，实现了最小的延迟，是资源有效的。然后，我们扩展它，通过使用堆栈矩阵的方法，浮点为基础的架构，实现了最小的有效延迟。我们的设计目标是为需要计算LU分解的应用程序开发高吞吐量和高能效的架构。我们分析了（1）高吞吐量，流水线浮点单元（不同深度的流水线和不同的性能）对体系结构的性能的影响，（2）算法级设计对系统范围内的能量耗散的影响。我们通过捕获算法和目标FPGA器件的架构细节来分析能量耗散。我们分析和比较我们的架构与FPGA上实现的最先进的架构的延迟，面积和能源。我们的设计比最先进的建筑节能10%-60%。
Summary form only given. We first develop a novel architecture for fixed-point LU decomposition of streaming input matrices, on FPGAs. Our architecture, based on a circular linear array, achieves the minimal latency and is resource-efficient. We then extend it, by using a stacked matrices approach, to a floating-point based architecture, which achieves the minimal effective latency. Our design objective was to develop high-throughput and energy-efficient architectures for applications, which require computing LU decomposition. We analyze (1) the impact of high-throughput, pipelined floating-point units (with different depths of pipelining and different performance) on the architecture's performance, and (2) the impact of algorithm level design on the system-wide energy dissipation. We analyze the energy dissipation by capturing algorithm and architectural details of the target FPGA device. We analyze and compare our architecture with a state-of-art architecture implemented on FPGAs with respect to latency, area and energy. Our designs achieve a 10%-60% reduction in energy over that of the state-of-art architecture.