Benchmarking weak memory models
Benchmarking weak memory models
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DOI：
10.1145/2851141.2851150
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发表时间：
2016-02
期刊：
影响因子：
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通讯作者：
Carl G. Ritson;Scott Owens
中科院分区：
文献类型：
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作者：
Carl G. Ritson;Scott Owens
为了实现良好的多核性能，现代微处理器采用弱内存模型，而不是强制顺序一致性。这为程序员提供了一个广泛的范围来选择如何通过系统共享内存实现线程间通信的各个方面。然而，这些选择同时带来语义和性能方面的后果，而且常常相互矛盾。在本文中，我们关注性能方面，并定义了一些技术，用于评估使用弱内存模型时各种选择的影响，例如在哪里放置围栏，以及使用哪些围栏。我们不试图判断某些策略是最好的或最有效的，而是提供一些技术，使程序员能够在识别和解决任何语义/性能权衡时理解性能含义。特别是，我们的技术支持合理选择宏基准，以便在使用弱内存模型时进行权衡。我们在ARMv8和POWERv7架构上的Linux内核和OpenJDK热点虚拟机的综合基准测试和实际应用程序上演示了我们的技术。
To achieve good multi-core performance, modern microprocessors have weak memory models, rather than enforce sequential consistency. This gives the programmer a wide scope for choosing exactly how to implement various aspects of inter-thread communication through the system's shared memory. However, these choices come with both semantic and performance consequences, often in tension with each other. In this paper, we focus on the performance side, and define techniques for evaluating the impact of various choices in using weak memory models, such as where to put fences, and which fences to use. We make no attempt to judge certain strategies as best or most efficient, and instead provide the techniques that will allow the programmer to understand the performance implications when identifying and resolving any semantic/performance trade-offs. In particular, our technique supports the reasoned selection of macrobenchmarks to use in investigating trade-offs in using weak memory models. We demonstrate our technique on both synthetic benchmarks and real-world applications for the Linux Kernel and OpenJDK Hotspot Virtual Machine on the ARMv8 and POWERv7 architectures.