A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier
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DOI：
10.1109/jssc.2019.2944831
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发表时间：
2019-11
影响因子：
5.4
通讯作者：
Aoyang Zhang;M. Chen
中科院分区：
文献类型：
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作者：
Aoyang Zhang;M. Chen
本文介绍了一种多次谐波开关 (SHS) 数字功率放大器 (PA) 架构，用于增强功率回退 (PBO) 效率，同时实现瓦级输出功率。所提出的相位交错架构提供了 PBO 区域中分谐波分量的固有消除，减轻了匹配网络的负担。所提出的多 SHS 方案可以进一步与 G 类操作相结合，以在 PBO 区域中创建更多数量的效率峰值。利用基于变压器的三路功率组合器和三重堆叠 D 类驱动器来获得瓦级输出功率。概念验证 PA 原型采用 65 nm CMOS 中的开关电容器 PA (SCPA) 架构实现，在 1.9 GHz 下实现了 30 dBm 峰值功率，在 0-、-3.5-、-7.0-、-9.5- 和 -12-dB PBO 时漏极效率为 45.9%/41.3%/35.3%/32.2%/24.2%，分别。在峰值平均功率比 (PAPR) 调制信号为 7.2 dB 的情况下，实时运行时的平均效率为 31.4%。
This article presents a multi-subharmonic switching (SHS) digital power amplifier (PA) architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output power. The proposed phase-interleaved architecture provides the inherent cancellation of the subharmonic components in the PBO region, alleviating the burden of the matching network. The proposed multi-SHS scheme can be further combined with a class-G operation to create a greater number of efficiency peaks in the PBO region. A transformer-based, three-way power combiner and a triple-stacking class-D driver are utilized to obtain watt-level output power. The proof-of-concept PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS and achieved 30-dBm peak power at 1.9 GHz, with 45.9%/41.3%/35.3%/32.2%/24.2% drain efficiency located at 0-, −3.5-, −7.0-, −9.5-, and −12-dB PBO, respectively. The average efficiency was 31.4% in real-time operation with a 7.2-dB peak-to-average power ratio (PAPR) modulated signal.